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build
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2024-11-20 06:28
initrd
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kernel
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modules.alias
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modules.alias.bin
1.55
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modules.builtin
9.49
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28.42
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modules.builtin.bin
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modules.builtin.modinfo
85.64
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modules.dep
762.22
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modules.dep.bin
1.01
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353
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modules.order
256.71
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modules.softdep
2.69
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modules.symbols
714.57
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intel_uncore.license=GPL intel_uncore.file=arch/x86/events/intel/intel-uncore intel_uncore.parm=uncore_no_discover:Don't enable the Intel uncore PerfMon discovery mechanism (default: enable the discovery mechanism). intel_uncore.parmtype=uncore_no_discover:bool microcode.parmtype=force_minrev:bool mmiotrace.parm=trace_pc:Record address of faulting instructions. mmiotrace.parm=nommiotrace:Disable actual MMIO tracing. mmiotrace.parm=filter_offset:Start address of traced mappings. mmiotrace.parmtype=trace_pc:bool mmiotrace.parmtype=nommiotrace:bool mmiotrace.parmtype=filter_offset:ulong sha512_ssse3.alias=crypto-sha384-avx2 sha512_ssse3.alias=sha384-avx2 sha512_ssse3.alias=crypto-sha384-avx sha512_ssse3.alias=sha384-avx sha512_ssse3.alias=crypto-sha384-ssse3 sha512_ssse3.alias=sha384-ssse3 sha512_ssse3.alias=crypto-sha384 sha512_ssse3.alias=sha384 sha512_ssse3.alias=crypto-sha512-avx2 sha512_ssse3.alias=sha512-avx2 sha512_ssse3.alias=crypto-sha512-avx sha512_ssse3.alias=sha512-avx sha512_ssse3.alias=crypto-sha512-ssse3 sha512_ssse3.alias=sha512-ssse3 sha512_ssse3.alias=crypto-sha512 sha512_ssse3.alias=sha512 sha512_ssse3.description=SHA512 Secure Hash Algorithm, Supplemental SSE3 accelerated sha512_ssse3.license=GPL sha512_ssse3.file=arch/x86/crypto/sha512-ssse3 crc32c_intel.alias=crypto-crc32c-intel crc32c_intel.alias=crc32c-intel crc32c_intel.alias=crypto-crc32c crc32c_intel.alias=crc32c crc32c_intel.license=GPL crc32c_intel.file=arch/x86/crypto/crc32c-intel crc32c_intel.description=CRC32c (Castagnoli) optimization using Intel Hardware. crc32c_intel.author=Austin Zhang <austin.zhang@intel.com>, Kent Liu <kent.liu@intel.com>